Advanced compute systems today make extensive use of 2.5D and 3D technology to scale performance. Fine grain connections between heterogeneous technologies offer many degrees of freedom for architects to design these compute systems. The next step in this HLSI evolution is to disaggregate the logic technology platform itself. This will bring us into the CMOS2.0 scaling paradigm offering many new opportunities for compute architecture innovations.

Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design-technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.

Despite considerable progress in energy efficiency, the electricity consumption of digital technologies continues to increase. These trends can be observed, for example, in data centers with the development of generative artificial intelligence, or in networks with the succession of mobile telephony generations, two examples at the heart of environmental controversies. Critical discourses generally mobilize the notion of rebound effect to indicate that energy efficiency does not limit energy consumption but instead encourages the growth of uses. Based on a literature review of rebound effects, we will show that this notion, as it is generally defined and understood, is not well suited to the case studies mentioned above. Our analysis will be based on the main actors involved in the deployment of these technologies, their objectives, and the strategies they implement to achieve them. This work highlights the limits of rebound effects as a basis for environmental critique and invites us to rethink how to frame the environmental challenges of digital technology.

Jacques Combaz is a CNRS research engineer at the VERIMAG laboratory in Grenoble. He worked on the design and verification of real-time systems using formal methods. In 2018, he redirected his research toward the environmental impacts of digital technologies. His work aims to go beyond the sole question of the life cycle of digital devices and infrastructures, and focuses in particular on rebound effects. He questions the frameworks used to assess the impacts of digital technology by adopting an interdisciplinary approach.

Today, the autonomy of devices deployed at the extreme edge, such as AirTags, is limited to only a few years. Remarkably, each of us relays the position of these tags anywhere in the world through the Bluetooth connection of our phones, enabling the formation of a virtually unlimited-range network. The latest generations of Wi-Fi routers are also capable of interacting in BLE mode. What, then, is preventing the large-scale deployment of intelligent sensor networks? This presentation discusses the latest developments achieved at CSEM and within the SwissChips framework, focusing on hardware solutions to remove the final wire, namely the charger, by revisiting energy harvesting, storage and distribution, sensor data acquisition, hierarchical processing using machine learning-based inference, and the transmission of structured data.

David Ruffieux has been with CSEM for over 30 years, where he has worked on timing and synthesizer IC design, developing atomic clocks, UWB positioning systems, BLE blocks and systems, XTAL and MEMS frequency references, temperature-compensated RTCs, and electromechanical oscillator-based sensors. He is also managing the ASICs for Edge activity, representing all chip design at CSEM. He has served on ISSCC and ESSERC technical program committees for over 10 years, including as chair of the RF & mm-wave track, and is now lecturing RF design at EPFL. He is also leading the IoT work package in the SwissChips special program, involving 60 FTEs and funded by the Swiss government.

Global Workspace Theory (GWT) is a leading account of human cognition and consciousness. In this view, a number of independent specialized modules connect to a shared central representation space; when a module is selected by attention, its contents are mobilized into the Global Workspace, and broadcast across the entire brain, resulting in a unified and integrated experience. Inspired by this framework, we have developed a deep learning architecture that captures key features of GWT: the Global Latent Workspace (GLW). I will present our GLW and its initial implementations, with promising applications in various AI domains. The model shows improvements in sample efficiency for multimodal representation learning. It can be leveraged for downstream classification and retrieval tasks. When an action module is connected to the GLW, the whole system exhibits affordance-like properties. The GLW is also beneficial as an input space for RL policy training: the policy is learned with fewer environment steps, and displays zero-shot cross-modal transfer abilities. Finally, augmenting the GLW with operation modules and an attention-controlled routing mechanism could open the way toward System-2 reasoning and sequential problem-solving.

Rufin VanRullen is a CNRS Research Director at CerCo (Toulouse) and holds an AI Research Chair at ANITI (Artificial and Natural Intelligence Toulouse Institute). He leads the ERC Advanced GLoW project, exploring novel deep-learning architectures based on the Global Workspace Theory. He has published more than 150 scientific papers, including influential articles on neural coding, object recognition, feed-forward vs. feedback processes, and attention.

Integrated circuits are now at the core of critical applications ranging from embedded and automotive systems to communication infrastructures, artificial intelligence, and connected objects. In this context, testing and reliability issues, historically focused on defect detection, robustness to variations, and fault tolerance, can no longer be considered independently from security and trust concerns. Indeed, many bridges exist between these domains: test mechanisms may become entry points for attacks, defects and faults may be exploited for malicious purposes, while some testing, monitoring, and characterization techniques can instead strengthen the detection of anomalies, hardware Trojans, or suspicious behaviors. This talk will provide an overview of the links between testability, reliability, hardware security, and trust in silicon.

Giorgio Di Natale received his PhD in Computer Engineering from Politecnico di Torino in 2003. A CNRS Research Director, he has been heading the TIMA laboratory in Grenoble since 2021. His research focuses on hardware security and trust, secure circuit design and test, reliability evaluation, fault tolerance, and VLSI circuit testing. Highly involved in the international scientific community, he has contributed to the organization of major conferences in his field, notably as General Chair of DATE 2020, Program Chair of DATE 2017, and member of the ETS Steering Committee. He is also Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also chaired the TTTC of the IEEE Computer Society; he is a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE.